The invention relates to receiving, via one data bus, at least one cache line of data along with a write request of a type that allows less than one cache line of data to be written to memory, and then placing, on another data bus, the data and a subsequent write request of a type that requires at least one cache line of data to be written.
Computer systems generally include one or more Peripheral Component Interface (PCI) buses that provide a special communication protocol between peripheral components, such as video controllers and network interface cards, and the computer system's main memory. When system memory and the peripheral components (PCI devices) reside on different buses, a bridge is required to manage the flow of data transactions between the two buses. PCI bus architecture is defined by the PCI Local Bus Specification, Revision 2.1 ("PCI Spec 2.1"), published in June 1995, by the PCI Special Interest Group, Portland, Oregon, incorporated by reference. PCI-to-PCI bridge architecture is defined by the PCI-to-PCI Bridge Architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0"), published in April 1994, by the PCI Special Interest Group, incorporated by reference.
Among the types of PCI transactions are writes to system memory. Memory write transactions, which under the PCI Spec 2.1 and PCI Bridge Spec 1.0 architectures are "posted" transactions (i.e., transactions that complete on the intiating bus before they complete on the target bus), include Memory Write (MW) and Memory Write and Invalidate (MWI) transactions. Memory Write (MW) transactions, involve the transfer of data ranging from a single byte to a multiple cache lines (eight double words) of data and require cache write back cycles from the CPU. Memory Write and Invalidate transactions require the transfer of an entire cache line of data and therefore eliminate the need for cache write back cycles. Memory Write transactions involving multiple dwords of data generally take longer to perform on the CPU host bus than Memory Write and Invalidate transactions because Memory Write cycles must transfer each dword of data individually and therefore experiences the inherent latency of the host bus with dword transfer. Memory Write and Invalidate transactions experience host bus latency only once for each cache line of data transferred.